Monday, January 16, 2017

Building a 68000 Single Board Computer - RAM and ROM Address Select (schematic page 4)


The selection of the individual RAM and EPROM components from the address decoder outputs is carried out by the circuit of page 4. Two-input OR gates combine one of the four device-select signals (SEL0* to SEL3*) from the address decoder with the appropriate data strobe (UDS* or LDS*) to produce the actual active-low chip-select inputs to the eight memory components on the CPU module.

The circuit is also responsible for overlaying the reset vector space onto the ROM memory space. When the RV* signal goes active-low while a reset vector is being fetched, the read/write memory at $00000000 to $00003FFF is disabled and the EPROM at $00008000 to $0000BFFF substituted.

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