Saturday, January 14, 2017

Building a 68000 Single Board Computer - Specifications of the TS2

Over the next few blog posts I'll go over the theory of operation of the TS2 68000 board. You'll want to open up the schematic diagram to follow the description.

This is based on the "Design Example Using the 68000" section of the book Microprocessor Systems Design 68000 Hardware, Software, and Interfacing, third edition, by Alan Clements. It has been adjusted to reflect my modified design.

First, a high level summary of the design goals and specifications of the board:

Specifications of the TS2

1. The TS2 uses a 68000 CPU.

2. It is built on a single circuit board.

3. The CPU card is capable of operating on its own. System testing is thus facilitated because other modules are not required to operate the CPU card in a stand-alone mode.

4. The original TS2 provided an external bus. This was omitted in my design as it was not required and reduced the chip count considerably.

5. The memory on the CPU card is static RAM and EPROM/EEPROM to avoid the complexity and associated difficulty of debugging dynamic RAM circuitry.

6. Full seven-level interrupt facilities are provided, but are optional. If included, these can support a level 7 interrupt (abort) switch, interrupts from the two ACIAs, and external interrupts.

7. Full address decoding is provided. The address space is compatible with the Motorola MEX68KECB Educational Computer Board (ECB) development system in order to facilitate the transfer of software between the TS2 and ECB.

8. The vector table at $00000000 to $000003FF is implemented in RAM, with the exception of the reset vectors which are mapped to the first 8 bytes of ROM (this will be described in more detail later).

9. The RAM is implemented by 8Kx8 CMOS devices to minimize the component count.

10. The ROM is implemented by 2764 type 8Kx8 EPROMs or 2864 type 8Kx8 EEPROMs (or equivalent CMOS devices).

11. The terminal (console) interface is through a serial port. A secondary port is also provided. Configuration is the same as in the ECB development system.

12. The module's local address and data buses have not been buffered as the CPU has adequate fanout.

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