Building a 68000 Single Board Computer - Reset, Halt, and Clock Control Circuits (schematic page 2)

See https://github.com/jefftranter/68000/blob/master/TS2/v2/ts2.pdf

Every CPU requires a certain amount of basic control circuitry to enable it to operate -- this circuitry includes its clock, reset, halt, and similar functions. Such circuitry can be designed largely independently of the rest of the system and is needed to perform even the simplest tests on the CPU. Therefore, we will design and test these circuits first.

Page 2 gives the diagram of the control circuitry surrounding the 68000, excluding the interrupt request inputs. The control of HALT* and RESET* is conventional. At power-on, a 555 timer configured as a monostable, U1, generates a single active-high pulse.

Open-collector buffers, U4C and U4D, apply the reset pulse to the 68000's RESET* and HALT* inputs, respectively. A manual reset generator is formed from two cross-coupled NAND gates, U3A and U3B, and applied to the reset lines by a further two open-collector buffers, U4A and U4B. An inverting buffer, U5A, gates the reset pulse from U1 onto the system bus as the active-low POR* (Power On Reset). This signal is used by other modules to clear circuits on power-up.

An LED, D1, is connected to the HALT* pin via a buffer. This LED is fitted to the front panel and confirms the reset operation. It also shows if the CPU has asserted HALT* because of a double bus fault.

The 68000 clock input is provided by an 8 MHz crystal-controlled clock in a DIP package. If desired, a lower speed clock oscillator can be used either for test purposes or to allow using a lower-speed 68000 chip.

The high impedance control circuits shown on page 1 are pulled up to the Vcc by resistors. Although pullup resistors are necessary on BR*, DTACK*, etc., the reader may be surprised to find them on AS*, UDS*, LDS*, and R/W*. They are required here because these pins are driven by tristate outputs in the 68000. When the 68000 relinquishes the bus all tristate lines are floated. To leave the state of these bus lines undefined is unwise, as a spurious bus cycle might possibly be generated in certain circumstances. A better course is to be safe rather than sorry. During the testing phase, some of the pullup resistors were temporary and used only for testing purposes, because they were connected to lines that will later be pulled up or down by totem-pole outputs. They appear so that the circuit can be tested independently of the rest of the system.

Testing the CPU control circuitry is very easy. The power on reset circuit is tested by attaching an oscilloscope probe to test point 1 (TP1), switching on the Vcc power supply, and observing the positive-going pulse. A negative-going pulse should be observed at the CPU's RESET* and HALT* pins. The manual reset pulse generator should force HALT* and RESET* low whenever the reset button is pushed.

An 8 MHz square wave should be observed at the CLK input to the CPU. All inputs pulled up to a logical 1 should be at a logical 1 state.

The next step is to install the 68000 and force the CPU to free-run. As no memory components have yet been fitted, the CPU must be fooled into thinking that it is executing valid bus cycles. To do this, DTACK* is temporarily connected to the AS* output. Whenever the 68000 starts a memory access by asserting AS*, DTACK* is automatically asserted to complete the cycle.

The 68000 is tricky to test in a free-running mode, because it generates an exception if a nonvalid op-code is detected. Should the 68000 then generate a second exception, the resulting bus fault will cause it to halt. Therefore, the 68000 must always see a valid op-code on its data bus. One way of doing this is to pull up (or down) the data bus lines with resistors to Vcc (or ground). Traditionally, CPUs are tested by placing a NOP (no operation) op-code on the data bus. The 68000 NOP code is $4E71 (i.e. %0100 1110 0111 0001). If this code is jammed onto the data bus, the 68000 will also use it for the stack pointer and reset vectors during the exception processing. Sadly, this code will lead to an address error. When the CPU reads the stack pointer from addresses $00000000 and $00000002 at the start of its reset exception processing, it obtains $4E714E71. Unfortunately this value is odd and generates an address exception. We need to use a dummy op-code that is even to allow the CPU to free-run. One suitable opcode is $0000 which corresponds to the instruction ORI.B #0,D0.

When a suitable op-code has been jammed into D00 to D15, the 68000 should free-run and a square wave observed on address pins A01 to A23. The frequency at pin Ai should be one half of that at Ai-1.