Building a 68000 Single Board Computer - RAM and ROM (schematic pages 5 and 6)

See https://github.com/jefftranter/68000/blob/master/TS2/v2/ts2.pdf

The use of 8Kx8 memory components permits the design of a memory with a very low component count and virtually no design effort. Page 5 gives the design of half of the components of the CPU module -- the others on page 6 (omitted in the Clements book) are arranged in exactly the same fashion but are enabled by different chip-select signals from the address decoder.

No further comment is required other than to point out that the EPROMs have their active-low output enables (OE*) driven by R/W* from the processor via an inverter. This action is necessary to avoid a bus conflict if a write access is made to EPROM memory space.

The original design used 2764 ultraviolet-erasable EPROMs. It is also compatible with 2864 electrically erasable EEPROMs. Either will work, but the latter are more easily erased and programmed. It can also use more modern CMOS memory devices (e.g. 27C64 and 28C64) which have lower current consumption.